Integrated circuit (IC) manufacturers are employing increasingly smaller dimensions and corresponding technologies to make smaller, high-speed semiconductor devices. Along with these advancements, the challenges of maintaining yield and throughput have also increased.
A semiconductor wafer typically includes dies (also known as chips before being sawed from the wafer) separated from each other by scribe lines. Individual chips within the wafer contain circuitry, and the dies are separated from each other by sawing. In a semiconductor fabrication process, semiconductor devices (e.g., an integrated circuit) on wafers must be continuously tested after some steps of the formation so as to maintain and assure device quality. Usually, a test circuit is simultaneously fabricated on the wafer along with the actual devices. A typical test circuit includes a plurality of test pads (commonly referred to test lines), which are electrically coupled to an external terminal through probe needles during the testing. The test pads may be located in the scribe lines. The test pads are selected to test different properties of the wafers, such as threshold voltages, saturation currents, and leakage currents. In addition to the test pads, there are other structures such as frame cells, dummy metal patterns, and the like, formed in the scribe lines.
After the testing of wafers through test pads, the wafers are sawed apart into dies, which sawing step is typically performed by using a blade. Since the test pads are formed of metals, the test pads have high resistance to the blade. On the other hand, there is a plurality of other materials that are also located in the scribe line, which include, for example, low-k dielectric layers. The low-k dielectric layers are porous and mechanically weak, and have very low resistance to the blade. Due to the difference in the mechanical strength between different materials that are sawed, lamination or crack may occur.